1. Field of the Invention
The invention relates in general to an etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation, and more particularly to an etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation applied to a silicon substrate.
2. Description of the Related Art
As the scale of integrated circuits decreases, the isolation process between the semiconductor devices to avoid current leakage or short circuit becomes more and more important. Conventionally, a local oxidation of silicon (LOCOS) isolation method is introduced to isolate semiconductor devices. The LOCOS isolation method mainly includes following steps. First, a pad oxide layer and a pad nitride layer are formed on a silicon chip. Next, the pad oxide layer and the pad nitride layer are etched to expose a part of the silicon chip. Then, a field oxide layer of silicon dioxide is formed by thermal oxidation. However, the silicon located on the edges of the pad oxide layer and the pad nitride layer is also oxidized to silicon dioxide by oxygen and moisture while forming the field oxide layer in the thermal oxidation process. The silicon dioxide on the edges is warped and forms “bird's beak,” which reduces the length of the active region. When the scale of semiconductor devices further decreases, the length of “bird's beak” affects the active region more significantly. As a result, the following manufacturing processes of the semiconductor device are affected seriously.
Therefore, a shallow trench isolation (STI) technology is developed recently. A trench is etched on a silicon chip first, and then silicon dioxide is filled in the trench for forming isolation between semiconductor devices. The pad oxide layer and the pad nitride layer are used as a mask layer while etching the trench. After the trench filling step and a planarization step, the mask layer is removed. However, when the mask layer is removed by wet etching, the etchant erodes the silicon or polysilicon of the silicon chip and damages the surface of the silicon chip. Additionally, after the mask layer is removed, nitride residuals on the silicon chip damage the surface of the silicon chip as well and lower the yield rate accordingly.
In order to avoid the so called “kooi effect” mentioned above and the accompanying white ribbon phenomenon, a method of utilizing a sacrificial oxide layer is developed. In general, the surface of the silicon chip is oxidized to from the sacrificial oxide layer. Then, the sacrificial oxide layer is removed for improving the surface quality of the silicon chip. However, the overall manufacturing time and steps are increased. Besides that, a shallow trench isolation technology without the pad nitride layer is developed to avoid the problems caused by wet etching the pad nitride layer. Nevertheless, other problems are brought up in this manner, e.g. the manufacturing process gets more complicated, the process step increases significantly, and the manufacturing cost is increased.
Therefore, there exists a requirement of solving the above problems without complicating the manufacturing process and increasing the cost.